The present invention relates generally to multiplexing data, and specifically to multiplexing asynchronous data into a synchronous format.
Speed capabilities of data networks are constantly increasing, and today Gigabit Ethernet networks, operating at 1 Gbps, are commercially available. In many cases, for example, where there is an existing lower-speed network in place, upgrading an existing network and all the existing infrastructure of the network involves considerable outlay in terms of time and money. To upgrade a network completely may involve, inter alia, changing network cabling, changing interface hardware devices between the cabling and existing computers, and changing hardware devices within hubs of the network. There is therefore a need for inexpensive hardware devices that can be used to interface between older, existing low-speed networks and new higher-speed networks.
Networks such as Fast Ethernet and Gigabit Ethernet networks are based on transferring data through the networks in the form of packets, wherein each packet comprises no more than a known packet size, expressed in terms of data-words. Between successive packets is a period of time, defined by a network protocol, during which data are not transferred. Fast Ethernet networks typically interface with physical media with 4 bit data-words, known as nibbles, in packets of up to 3036 nibbles, the nibbles being clocked at a nominal 25 MHz thereby transferring data at a nominal 100 Mbps. Gigabit Ethernet networks typically operate in packets of up to 1518 bytes, the bytes being clocked at a nominal 125 MHz, thereby transferring data at a nominal 1 Gbps. Clocks which are used to transfer the data within the network, while nominally of a fixed frequency, are allowed to vary in frequency by a permitted tolerance. Thus, for Fast Ethernet networks the permitted clock frequencies are 25 MHz xc2x10.01%, and for Gigabit Ethernet networks the permitted frequencies are 125 MHz xc2x10.01%.
Problems associated with clock rate differences within networks are well known in the art. For example, clock recovery from received data is a recognized method for generating a clock synchronous with the data. Other methods for generating a synchronous clock from an asynchronous clock, or for producing a clock signal of a specific shape and duty cycle from an arbitrarily-shaped input clock, are also known in the art.
U.S. Pat. No. 5,278,456, to Bechade et al., whose disclosure is incorporated herein by reference, describes a process for generating a clock signal with a specific duty cycle from an input clock signal with a variable duty cycle. The generated clock signal is synchronous with the input clock signal, so that the signals have exactly the same frequency.
U.S. Pat. No. 5,488,639, to MacWilliams et al., whose disclosure is incorporated herein by reference, describes a method for synchronizing an asynchronous signal, such as a read signal, to a reference clock signal. The method relates to synchronizing the phase of the asynchronous signal with the phase of the reference clock signal.
It is an object of some aspects of the present invention to provide methods and apparatus for synchronizing asynchronous packets of data.
It is a further object of some aspects of the present invention to provide methods and apparatus for multiplexing asynchronous packets of data from a plurality of sources.
In preferred embodiments of the present invention, a multiplexer feeds data from a plurality of electronic data-word sources, operating at low data rates, into a common line of a high data-rate network. The sources typically provide packets of data-words at a common data-rate, for example at 100 Mbps, from respective low data-rate networks, but operate asynchronously with respect to one another. The term data-word is to be understood herein as comprising any integral number of bits of data. The multiplexer combines the data-words and feeds the combination to a high data-rate interface as a synchronous data stream, for example, at 1 Gbps. The high data-rate interface then feeds the combination as packets into the high data-rate network. In order to multiplex the asynchronous data received from the plurality of sources, the data-words from each source are fed through a respective series of latches, which act as storage buffers. The latches in each series are clocked so that the data-words are available for multiplexing at an output latch in the series in the required synchronization for multiplexing at the high data rate, despite the asynchrony of the low data-rate clocks and drift between the different clocks, and substantially without loss of data-words in the multiplexing process.
Multiplexing the outputs of the plurality of low data-rate sources into the high data-rate network has a number of advantages:
The high data-rate network can be installed in addition to the existing low data-rate network, and the infrastructure of the low data-rate network can continue to be used.
By using one multiplexer to feed data from the plurality of generators into the high data-rate network, overall pin count in an interface between the sources and the high data-rate network is substantially reduced compared to the pin count which would be needed if separate interfaces were used for the different sources.
In some preferred embodiments of the present invention, data from the plurality of sources is generated initially as data-words of 4 bits, and the 4-bit data-words are combined into bytes of 8 bits in a first latch. Two or more subsequent latches are used as described above to buffer and then synchronize the bytes to the high data rate.
There is therefore provided, in accordance with a preferred embodiment of the present invention, apparatus for multiplexing electronic data-words provided by a plurality of input sources operating in accordance with respective input clocks, which may be mutually asynchronous, to a common output operating in accordance with a system clock, the apparatus including:
delay circuitry, which generates a plurality of select signals responsive to the system clock, corresponding respectively to the plurality of input sources;
a plurality of synchronizers respectively associated with the plurality of input sources, each synchronizer including a series of memory buffers through which data-words from the respective input source are transferred, the series of memory buffers including at least:
an input buffer, which receives the data-words from the respective input source in accordance with the respective input clock; and
an output buffer, which provides the data-words for output in accordance with the corresponding select signal; and
a multiplexer which receives the data-words from the output buffers of the plurality of synchronizers responsive to the respective select signals, and which combines the data-words into the common output in accordance with the system clock.
Preferably, each series of memory buffers includes an intermediate buffer which receives the data-words from the corresponding input buffer and which transfers the data-words to the corresponding output buffer responsive to the corresponding select signal.
Preferably, the intermediate buffer transfers the data-words to the corresponding output buffer at a time determined by a corresponding intermediate phase which is a function of a phase of the corresponding select signal and a phase of the corresponding input clock.
Preferably, the corresponding intermediate phase is a mean of the phase of the corresponding select signal and the phase of the corresponding input clock when a difference between the phase of the corresponding select signal and the phase of the corresponding input clock is greater than or equal to 180xc2x0, and the corresponding intermediate phase is the mean plus 180xc2x0 when the difference between the phase of the corresponding select signal and the phase of the corresponding input clock is less than 180xc2x0.
Further preferably, each synchronizer includes a controller which generates respective clock signals to control transfer of the data-words from the corresponding input buffer and the corresponding intermediate buffer and the corresponding output buffer responsive to the corresponding select signal and the corresponding input clock and the system clock.
Preferably, the delay circuitry generates a sequence of synchronizing pulses each of which is applied to the plurality of synchronizers during a time period when the data-words are not being received from the output buffers, so as to zero out clock drift.
Preferably, the delay circuitry generates the synchronizing pulses within a period which is a function of a nominal asynchrony of the plurality of input clocks, so that the output data-words and corresponding input data-words differ in phase by no more than a predetermined maximum phase deviation.
Further preferably, the multiplexer is coupled to transfer the common output to a packet-switched network, and the sequence of synchronizing pulses is generated responsive to a packet synchronization signal in the network.
Preferably, the common output includes an output which operates in accordance with a Gigabit Ethernet standard, and the plurality of input sources includes at least some input sources which operate in accordance with a Fast Ethernet standard.
Preferably, each of the synchronizers that is coupled to receive input in accordance with the Fast Ethernet standard includes a data assembly buffer, in which two four-bit data-words are combined into one eight-bit data-word for output in accordance with the. Gigabit Ethernet standard.
Further preferably, the plurality of select signals includes a sequence of select signals such that a respective select signal in the sequence is provided to each of the plurality of synchronizers.
Preferably, the memory buffers include latches arranged to transfer data from one to another in sequence and mutually clocked so that each data-word received by a given one of the latches is transferred to the next latch in the sequence before the given latch receives the next data-word.
There is further provided, in accordance with a preferred embodiment of the present invention, a method for multiplexing a plurality of electronic data-words provided by a plurality of input sources operating in accordance with respective input clocks, which may be mutually asynchronous, to a common output operating in accordance with a system clock, the method including:
generating a plurality of select signals responsive to the system clock, corresponding respectively to the plurality of input sources;
receiving the data-words from the input source in respective input buffers in accordance with the respective input clocks;
conveying the data-words in the input buffers to corresponding output buffers such that the data-words are available for output from the output buffers in accordance with the respective select signals; and
multiplexing the data-words from the output buffers responsive to the select signals so as to provide the common output responsive to the system clock.
Preferably, conveying the data-words includes conveying the data-words from the input buffers to respective intermediate buffers which transfer the data-words to the corresponding output buffers responsive to the respective select signals.
Preferably, conveying the data-words includes generating an intermediate clock phase at which the data-words are to be transferred by the intermediate buffers as a mean of a phase of the corresponding select signal and a phase of the corresponding input clock when a difference between the phase of the corresponding select signal and the phase of the corresponding input clock is greater than or equal to 180xc2x0, and generating each of the corresponding phases as the mean plus 180xc2x0 when the difference between the phase of the corresponding select signal and the phase of the corresponding input clock is less than 180xc2x0.
Preferably, the method includes generating a sequence of synchronizing pulses each of which is applied to the plurality of synchronizers during a time period when the data-words are not being received from the output buffers, so as to zero out clock drift.
Further preferably, generating the sequence of synchronizing pulses includes generating the pulses with a period which is a function of a nominal asynchrony of the plurality of input clocks, so that the output data-words and corresponding input data-words differ in phase by no more than a predetermined maximum phase deviation.
Preferably, multiplexing the data-words includes outputting the data-words in accordance with a Gigabit Ethernet standard, and receiving the data-words includes receiving the data-words from at least some input sources operating in accordance with a Fast Ethernet standard.
Preferably, generating the plurality of select signals includes generating a sequence of select signals such that a respective select signal in the sequence is provided to each of the plurality of synchronizers.